The present invention is directed to processes for the fabrication of semiconductor integrated circuit devices and, more particularly, to the formation of metal interconnections used in semiconductor integrated circuit devices.
As semiconductor device features shrink and the number of wiring layers increases, irregularities of any size in the surface of a respective layer translate to the subsequently deposited, overlying layers and create even greater irregularities in the surfaces of the overlying layers. The surface irregularities distort the heights and shapes of any features formed on the surfaces of the overlying layers and make printing on and alignment of underlying to overlying layers more difficult. Often, the height variation in the surfaces of the overlying layers exceed the depth of focus of the photolithographic tools so that it is essentially impossible to print the intended features over the entire surface or to align a printing mask to previous levels.
To create an essentially flat or planar surface at each layer so that shapes are printed with high dimensional and geometric accuracy, planarization processes are employed. One such known planarization process is to employ a “damascene” process that uses chemical mechanical polishing (CMP). In the “damascene” process, one or more dielectric layers are deposited over the device dielectric layer, and openings are formed in the dielectric layers. A conductor material is deposited over the dielectric layer and in the openings. Chemical mechanical polishing is then employed to planarize the surface, namely to cause the top surface of the conductor material to be at the same height as the top surface of the dielectric layer, so that the conductor material is “inlaid” in the dielectric layer.
For a single level of interconnections, a “single damascene” process is used. A thin channel stop layer is deposited over a device dielectric layer and serves as an etch stop layer. A photoresist layer is then deposited on the first channel stop layer and photolithographically patterned, and the exposed portions of the first channel stop layer are then anisotropically etched to provide openings to the device contact regions. A channel dielectric layer is then formed atop the first channel stop layer. Typically, when one of the channel dielectric layer or the channel stop layer is an oxide material, such as silicon dioxide (SiO2), the other one of the two layers is a nitride, such as silicon nitride (SiN), so that selective etching may be used. The channel dielectric layer is then subject to further photolithographic patterning and etching steps to form channel openings therein. A thin adhesion layer, such as tantalum nitride (TaN), titanium nitride (TiN) or tungsten nitride (WN), may then be deposited on the channel dielectric layer to line the channel openings or lines and ensure good adhesion of any subsequently deposited material to the channel dielectric layer.
A conductor material, such as copper (Cu), tantalum (Ta), titanium (Ti) or tungsten (W), is then formed over the channel dielectric layer and fills the openings in the channel dielectric layer. A chemical mechanical polishing step is then carried out to remove any portions of the conductor material that are above the top surface of the channel dielectric layer, thereby forming conductor lines in the channel dielectric layer, and to “planarize” the top surface of the two layers. A “capping” layer may then be deposited as a final layer.
Alternatively, for more complex devices, a “dual damascene” technique is employed. A via stop layer is deposited instead of the capping layer, and a via dielectric layer is then deposited atop the via stop layer. When either the via stop layer or the via dielectric layer is an oxide material, the other one of the two layers is a nitride material so that the two layers may be selectively etched.
Thereafter, a further channel stop layer and a further channel dielectric layer are formed atop the via dielectric layer. Again, when one of the further channel dielectric layer or the further channel dielectric layer is an oxide material, the other one is a nitride material so that the two layers can be selectively etched. The further channel dielectric layer, the further channel stop layer, the via dielectric layer and the via stop layer are then subject to further photolithographic processing and etching to form vias and further channel openings or lines in the layers. A thin adhesion layer may then be deposited on the further channel dielectric layer to line the further channel openings and the via openings. A barrier or liner layer is then deposited on the adhesion layer and lines the adhesion layer in the further channel openings and the vias. Next, a further conductor material is deposited over the channel dielectric layer and fills the further channel openings and the vias.
A CMP process is then employed to remove the part of the further conductor material and the barrier or liner layer that is above the further channel dielectric layer to form further conductor lines. A “capping” layer may then be formed over the further channel lines as a final layer. Alternatively, an etch stop layer is formed and further processing is carried out to form additional levels of conductor lines and vias. Individual and/or multiple levels of single and dual damascene structures may be formed for single and multiple levels of conductor lines and vias, also known as interconnects.
To carry out the above CMP processes, a conventional CMP apparatus typically includes a rotating table having a polishing pad disposed thereon and includes a wafer carrier that holds a wafer. The wafer is held by a platen in an inverted position against the polishing pad. A predetermined pressure is exerted on the wafer against the polishing pad, and a slurry is applied between the wafer and the polishing pad. In operation, the polishing pad and the wafer rotate in relation to one another. The wafer is polished by mechanical abrasion from the polishing pad and from particles in the slurry and by chemical action from the slurry on the polishing pad.
Apparatus for polishing semiconductor wafers are well known in the art. Typically, two polishing pads are used. The semiconductor wafer is first polished using a hard pad on a primary rotating table. The hard pad planarizes the wafer surface by removing the material on higher raised areas faster than in the lower areas. The wafer is then polished using the soft pad to remove any residual material or slurry residue on the wafer surface and to improve the uniformity of the wafer.
The known chemical mechanical polishing systems, however, have the disadvantage that the rate at which conductor material is removed is faster in higher pattern density regions, namely in regions with a higher density of conductor lines, than in lower pattern density regions. As a result, when all of the conductor material and liner layer that is atop the channel dielectric layer in the higher pattern density regions is removed, a portion of the conductor material that is atop the channel dielectric layer in the lower pattern density regions, as well as the liner layer, remains. To ensure that all of the conductor material and liner layer that is atop the channel dielectric layer in the lower pattern density regions is removed, the higher pattern density regions must be “overpolished.” Furthermore, material removal during CMP is never completely uniform across the entire wafer, even for areas of the wafer that exhibit the same pattern density. Thus, some areas of the wafer need to be polished longer in comparison to other areas in order to remove all of the metal overburden. The overpolishing often removes a part of the conductor lines as well as some of the channel dielectric layer, an effect known as “dishing”. The removal of the material from the conductor lines, however, is often undesirable because the electrical performance of the devices may be affected by the amount of conducting material in the conductor lines. Therefore, the CMP step must be of sufficient length to remove all of the overlying conductor material and liner layer in the lower pattern density regions but must be short enough to avoid excessive dishing in the higher density regions that would degrade electrical performance.
Newer generations of faster devices include conductor lines that are smaller and narrower and which are spaced more closely together in the higher density regions. The smaller and narrower lines and the increased line density further reduce the CMP process window between an inadequate removal of the conductor material in the lower pattern density regions and excessive dishing in the higher density regions. In some processes, the process window is eliminated altogether and results in complete removal of the conductor lines in some of the higher density regions, such as at the edge of the wafer. As a result, the devices in these regions are unusable, thereby reducing the process yield and increasing manufacturing costs.
It is therefore desirable to provide a chemical mechanical polishing process that completely removes the overlying conductor material and liner layer in the lower pattern density regions without avoid excessive dishing in the higher density regions.